URL https://opencores.org/ocsvn/uart16550/uart16550/trunk

Subversion Repositories uart16550

[/] [uart16550/] [trunk/] [sim/] [rtl_sim/] [run/] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5570d 05h	/uart16550/trunk/sim/rtl_sim/run/
95	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead only when TX FIFO is empty. This causes testcases not to finish.	tadejm	7379d 11h	/uart16550/trunk/sim/rtl_sim/run/
14		gorban	8336d 23h	/uart16550/trunk/sim/rtl_sim/run/