URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] - Rev 8

Rev	Log message	Author	Age	Path
8	Updated core description document to include Lattice device synthesis results.	motilito	4804d 02h	/uart2bus/trunk/
7	Updated the Scilab script for Scilab 5.3 version. Previous versions might not work.	motilito	4825d 11h	/uart2bus/trunk/
6	Commit VHDL description source with basic test benches	smuller	5074d 20h	/uart2bus/trunk/
5	Add structure for VHDL (verilog similar tree).	smuller	5086d 14h	/uart2bus/trunk/
4	Corrected some problems in the binary mode protocol test bench. Updated documentation.	motilito	5181d 12h	/uart2bus/trunk/
3		motilito	5227d 18h	/uart2bus/trunk/
2	Uploaded the initial project version.	motilito	5227d 19h	/uart2bus/trunk/
1	The project and the structure was created	root	5230d 13h	/uart2bus/trunk/