URL https://opencores.org/ocsvn/uart2bus_testbench/uart2bus_testbench/trunk

Subversion Repositories uart2bus_testbench

[/] [uart2bus_testbench/] - Rev 10

Rev	Log message	Author	Age	Path
10	add maximum simulation time + refine the reporting phase	HanySalah	2544d 06h	/uart2bus_testbench/
9	Change the verbosity of passed test message to be UVM_HIGH + add the reporting message in the report phase in testfile	HanySalah	2544d 07h	/uart2bus_testbench/
8		HanySalah	2673d 13h	/uart2bus_testbench/
7	Remove run tests from topmodule	HanySalah	3032d 04h	/uart2bus_testbench/
6		HanySalah	3032d 04h	/uart2bus_testbench/
5	remove coverage requirement section	HanySalah	3032d 16h	/uart2bus_testbench/
4		HanySalah	3032d 17h	/uart2bus_testbench/
3		HanySalah	3032d 17h	/uart2bus_testbench/
2	Initial Version	HanySalah	3058d 07h	/uart2bus_testbench/
1	The project and the structure was created	root	3058d 20h	/uart2bus_testbench/