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[/] [usb_dongle_fpga/] [tags/] [version_1_4/] - Rev 53

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Rev Log message Author Age Path
53 New directory structure. root 5579d 07h /usb_dongle_fpga/tags/version_1_4/
21 This commit was manufactured by cvs2svn to create tag 'version_1_4'. 5957d 06h /tags/version_1_4/
20 Fix'ed TAR cycle second part this is not critical update nuubik 5957d 06h /trunk/
19 Fix'ed cycle type init code copy/pase mistake nuubik 5957d 08h /trunk/
18 Fixed in reset init of some trigers (this should not have generated extra hardware in FPGA but just to be on the safe side) nuubik 5958d 08h /trunk/
17 changed version code to 04 and added spy mode by puting jumpers on header and also implemented LPC Firmware Hub read to enable this booting mode (selectable by header jumper see documentation) nuubik 5958d 08h /trunk/
16 Synchronisation with OpenCores release nuubik 6091d 05h /trunk/
15 changed version code to 03 and disabled spy mode on juper setting 00 (this disabled booting but postcode IO write was displayed) nuubik 6208d 07h /trunk/
14 added comment on POR time influence when booting from LPC dongle nuubik 6220d 07h /trunk/
12 Added windows py bindings check with nice info print with link to installer nuubik 6322d 00h /trunk/
11 one ; in line end possible runtime error nuubik 6322d 00h /trunk/
10 fixed a typo nuubik 6325d 22h /trunk/
9 Made failing on port open retry nuubik 6325d 22h /trunk/
8 Added PCB level test options nuubik 6326d 06h /trunk/
7 Fixed pin modes and resyntesized nuubik 6326d 06h /trunk/
6 Fixed Cyclon part no in datasheets and drawings nuubik 6363d 03h /trunk/
4 Changed LED SM front to falling to avoid large current switches at the same time as data nuubik 6388d 23h /trunk/
3 Changed outputs to LVCMOS and lowered drive current to 2mA to avoid noise on longer tracs and fast switching speeds nuubik 6388d 23h /trunk/
2 Initial global code commit nuubik 6403d 06h /trunk/
1 Standard project directories initialized by cvs2svn. 6403d 06h /trunk/

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