URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] [v586/] - Rev 117

Rev	Log message	Author	Age	Path
117	reset polarity in mig_b.prj for ddr2 was wrong , should be high	ultro	2839d 04h	/v586/
116	fix path of the axi rom module	ultro	2852d 23h	/v586/
115	update for synth slack	ultro	2853d 17h	/v586/
114	update cosmetic	ultro	2853d 18h	/v586/
113	updates to take acu appart	ultro	2853d 18h	/v586/
112	Added the prj missing files	ultro	2857d 07h	/v586/
111	added comment	ultro	2873d 17h	/v586/
110	updated MCS files to be downloaded to nexys4 DDR	ultro	2873d 17h	/v586/
109	update for nexys 4 ddr	ultro	2873d 17h	/v586/
108	update xdc for nexys 4 ddr	ultro	2873d 17h	/v586/
107	crossbar update	ultro	2873d 17h	/v586/
106	update core netlist	ultro	2873d 17h	/v586/
105	migration nexys ddr	ultro	2873d 19h	/v586/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2880d 18h	/v586/
103	commit top for 128mbyte nexys4 ddr version	ultro	2890d 08h	/v586/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2890d 08h	/v586/
101	add ddr interface mig7 xilinx xci ip	ultro	2890d 22h	/v586/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2890d 22h	/v586/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	2932d 06h	/v586/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	2932d 16h	/v586/