URL https://opencores.org/ocsvn/v586/v586/trunk

Subversion Repositories v586

[/] [v586/] [trunk/] - Rev 105

Rev	Log message	Author	Age	Path
105	migration nexys ddr	ultro	2870d 17h	/v586/trunk/
104	iadd rstgen and clk wiard for ddr nexys4 TOP	ultro	2877d 17h	/v586/trunk/
103	commit top for 128mbyte nexys4 ddr version	ultro	2887d 06h	/v586/trunk/
102	committed 128mbytes boot code for nexys4 ddr	ultro	2887d 06h	/v586/trunk/
101	add ddr interface mig7 xilinx xci ip	ultro	2887d 20h	/v586/trunk/
100	add crossbar for nexys4 ddr with 128megabyte ram window	ultro	2887d 20h	/v586/trunk/
99	remove phy_intn from xdc constraints as it is not used inside design wi th etherlite.	ultro	2929d 05h	/v586/trunk/
98	update tbench and add mii to rmii converter ip from xilinx	ultro	2929d 14h	/v586/trunk/
97	update periph and TOP	ultro	2929d 15h	/v586/trunk/
96	update periph , uart is not inside	ultro	2929d 15h	/v586/trunk/
95	update boot.mem accordingly to test.s cleanup	ultro	2931d 18h	/v586/trunk/
94	clean up test.s	ultro	2931d 18h	/v586/trunk/
93	added stub for keyboard	ultro	2932d 07h	/v586/trunk/
92	added doc	ultro	2932d 08h	/v586/trunk/
91	update netlists cosmetics	ultro	2932d 20h	/v586/trunk/
90	updated cosmetic periph.v	ultro	2932d 21h	/v586/trunk/
89	add 3x rtl files	ultro	2932d 23h	/v586/trunk/
88	remove axi ip standalone	ultro	2932d 23h	/v586/trunk/
87	update rtl for boot.mem	ultro	2932d 23h	/v586/trunk/
86	update tbench	ultro	2932d 23h	/v586/trunk/