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URL https://opencores.org/ocsvn/virtex7_pcie_dma/virtex7_pcie_dma/trunk

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[/] [virtex7_pcie_dma/] - Rev 19

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Rev Log message Author Age Path
19 * driver/README updated oussamak 3191d 06h /virtex7_pcie_dma/
18 Changed:
* Added drivers
* Added Wupper tools for debugging
* Added card ID register		 oussamak 3191d 08h /virtex7_pcie_dma/
17 Changed name of toplevel, to make tree consistent oussamak 3205d 10h /virtex7_pcie_dma/
16 MODIFED:
-- top level name to wupper_oc (including scripts)		 aborga 3255d 04h /virtex7_pcie_dma/
15 MODIFIED:
-- Renamed core to Wupper (vhdl files)
-- Changed width of interrupt enable to number_of_interrupts		 fransschreuder 3255d 05h /virtex7_pcie_dma/
14 RENAMED:
-- simulation folder		 aborga 3255d 06h /virtex7_pcie_dma/
13 RENAMED:
-- script		 aborga 3255d 06h /virtex7_pcie_dma/
12 Fixed http://opencores.org/bug,view,2524 fransschreuder 3330d 06h /virtex7_pcie_dma/
11 MODIFIED:
-- updated documentation		 aborga 3343d 04h /virtex7_pcie_dma/
10 Changed:
LOC => Package_pin		 fransschreuder 3353d 04h /virtex7_pcie_dma/
9 Added actual version information (Build date and svn revision) in BOARD_ID register fransschreuder 3382d 02h /virtex7_pcie_dma/
8 Changed:
* Added support for circular DMA (wrap around)
* Fixed Read / Write interrupts		 fransschreuder 3382d 09h /virtex7_pcie_dma/
7 Changed:
* Simplified address calculation to relax timing
* Changed slow register clock from 40 MHz to 250/6=41.667MHz to relax timing
* Omit need of external clock crystal on the board (all clocks are now derived from the 100MHz pcie refclk
* Added support for the High tech Global HTG710 board		 fransschreuder 3422d 05h /virtex7_pcie_dma/
6 Changed:
* fixed bug #1 First read of registers sometimes fails. Added extra pipeline stage on read / write enable
* Fixed missing signals in sensitivity list		 fransschreuder 3428d 03h /virtex7_pcie_dma/
5 Changed:
* Added two registers to test interrupts vectors 2 and 3
* Added a register to read generic constants to show number of interrupts / number of descriptors
* fixed consistency of generic default values among different design units
* fixed route of pll_locked / register map record, to allow non-flattening of synthesis		 fransschreuder 3429d 07h /virtex7_pcie_dma/
4 fixed a typo in the interrupt table documentation fransschreuder 3441d 03h /virtex7_pcie_dma/
3 Created:
First commit of the full PCIe DMA Core
Including:
-Firmware
-Vivado .tcl scripts
-Questasim simulation scripts
-Documentation (Latex / Doxygen script)		 fransschreuder 3441d 04h /virtex7_pcie_dma/
2 Added firmware directory fransschreuder 3444d 02h /virtex7_pcie_dma/
1 The project and the structure was created root 3462d 21h /virtex7_pcie_dma/

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