URL https://opencores.org/ocsvn/wb2axip/wb2axip/trunk

Subversion Repositories wb2axip

[/] [wb2axip/] - Rev 11

Rev	Log message	Author	Age	Path
11	Updated the bench/formal properties SVN will now ignore the build files associated with this directory: .smt2, .yslog, *.vcd	dgisselq	2368d 01h	/wb2axip/
10	Added files to flush out the formal proof capability	dgisselq	2368d 01h	/wb2axip/
9	Added a formal directory	dgisselq	2368d 01h	/wb2axip/
8	The WB to AXI translator wrks and works well. A proof of this will be added shortly.	dgisselq	2368d 01h	/wb2axip/
7	Simplified.	dgisselq	2685d 01h	/wb2axip/
6	IT WORKS!!! (On non-pipelined data--havent tested it on pipelined stuff .. yet)	dgisselq	2812d 21h	/wb2axip/
5	Adjusted variable names to match the spec and the MIG.	dgisselq	2817d 12h	/wb2axip/
4	Adjusted the core quickly so it should work for 128-bit wide wishbone busses as well as 32-bit wide busses.	dgisselq	2817d 18h	/wb2axip/
3	Fixed the Verilator compile-time bugs. Still haven't tested the core.	dgisselq	2817d 18h	/wb2axip/
2	Initial check in. Core not (yet) tested, verified, or validated.	dgisselq	2817d 19h	/wb2axip/
1	The project and the structure was created	root	2817d 19h	/wb2axip/