URL https://opencores.org/ocsvn/xge_mac/xge_mac/trunk

Subversion Repositories xge_mac

[/] [xge_mac/] [trunk/] [rtl/] - Rev 26

Rev	Log message	Author	Age	Path
26	Fix packet count	antanguay	4206d 21h	/xge_mac/trunk/rtl/
25	Timing improvements, reduced FIFO size from 1024 to 512	antanguay	4206d 23h	/xge_mac/trunk/rtl/
24	Use FIFO's for statistics clock domain crossing	antanguay	4207d 00h	/xge_mac/trunk/rtl/
23	Adding basic packet stats	antanguay	4207d 06h	/xge_mac/trunk/rtl/
22	Added prototype system verilog testbench	antanguay	4209d 03h	/xge_mac/trunk/rtl/
21	Improvements for timing, adding alternate FIFO design using XIL define	antanguay	4209d 03h	/xge_mac/trunk/rtl/
20	Updates for Xilinx synthesis	antanguay	4498d 22h	/xge_mac/trunk/rtl/
12	Change interface to big endian, added serdes examples to testbench	antanguay	5285d 05h	/xge_mac/trunk/rtl/
11	Fixed clock crossing	antanguay	5391d 03h	/xge_mac/trunk/rtl/
10	Added details to spec	antanguay	5488d 22h	/xge_mac/trunk/rtl/
7	New directory structure.	root	5563d 14h	/xge_mac/trunk/rtl/
6	Updated spec. Added mod[2:0] signals. Timing improvements.	antanguay	5839d 22h	/trunk/rtl/
5	Fixed compilation	antanguay	5845d 23h	/trunk/rtl/
2	Initial revision	antanguay	5846d 02h	/trunk/rtl/