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Rev Log message Author Age Path
26 Added test data for 32k memory.
Added GTKW configuration file.		 lcdsgmtr 3167d 09h /xucpu/
25 Problem with memory: created conditional generate based upon data width
instead of address width.		 lcdsgmtr 3167d 09h /xucpu/
24 Starting tracing through the component hierarchy initialisation. lcdsgmtr 3167d 09h /xucpu/
23 Currently moved test bench to 10 bit address.
Created spreadsheet for filling memory with random data.
When testing, memory is apparently not initialised.		 lcdsgmtr 3167d 09h /xucpu/
22 Update on makefile, because some parts are in other files. lcdsgmtr 3167d 09h /xucpu/
21 Since all BRAM is unified in one component, this testbench is not necessary
anymore.		 lcdsgmtr 3167d 09h /xucpu/
20 Update RAM package to allow for 15-bit address.
Update test bench to use address width parameter.		 lcdsgmtr 3167d 09h /xucpu/
19 Makefile for building memory block testbench. lcdsgmtr 3167d 09h /xucpu/
18 Ignore work files from GHDL. lcdsgmtr 3167d 09h /xucpu/
17 Moving the generic block ram component piece by piece to a better
implementation.		 lcdsgmtr 3167d 09h /xucpu/
16 Re-write of memory in function of initial array memory blocks. lcdsgmtr 3167d 09h /xucpu/
15 Unification of all RAM parts into one interface. lcdsgmtr 3167d 09h /xucpu/
14 Simple implementation project. lcdsgmtr 3299d 08h /xucpu/
13 Updated smallest Xilinx configuration. lcdsgmtr 3299d 08h /xucpu/
12 Update Xilinx configurations. lcdsgmtr 3299d 08h /xucpu/
11 Successful run of the simulation. Correct results. lcdsgmtr 3299d 10h /xucpu/
10 Correct build with GHDL. lcdsgmtr 3299d 10h /xucpu/
9 This makes sure that this GHDL configuration analyses correctly. lcdsgmtr 3299d 10h /xucpu/
8 Rebuilding the configuration to build the first system using GHDL. lcdsgmtr 3300d 08h /xucpu/
7 Moved package for initialising memory also to src. lcdsgmtr 3300d 08h /xucpu/

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