| Rev |
Log message |
Author |
Age |
Path |
| 113 |
Lots of updates, mostly focused on getting the XuLA board and CPU able to pass
a comprehensive test suite. At this point, everything passes and logic usage
is down even. Among the few changes includes the "break" bit in the uCC
register, used to indicate a switch to supervisor mode occurred as a result
of a user break, and the ability for the supervisor to clear the instruction
cache. |
dgisselq |
2881d 16h |
/xulalx25soc/trunk/bench/ |
| 112 |
Provides a simulated UART capability to the busmaster_tb simulation. |
dgisselq |
2883d 21h |
/xulalx25soc/trunk/bench/ |
| 107 |
Minor change. |
dgisselq |
2890d 10h |
/xulalx25soc/trunk/bench/ |
| 106 |
Minor, inconsequential changes. |
dgisselq |
2890d 10h |
/xulalx25soc/trunk/bench/ |
| 96 |
Now accepts an SD-Card backing file, so that SD-Card reads *and* writes can be
tested. |
dgisselq |
2913d 14h |
/xulalx25soc/trunk/bench/ |
| 95 |
Added write capability to the SD-SPI simulator. |
dgisselq |
2913d 14h |
/xulalx25soc/trunk/bench/ |
| 94 |
Fixes a bug which had caused the device to die artificially and early, just
simply because the program connecting to the simulator shut its pipe down before
getting our last message. We now ignore this signal and continue. |
dgisselq |
2913d 14h |
/xulalx25soc/trunk/bench/ |
| 75 |
Added simulation capability for the SD-Card, as well as debugging output for the
DMA. (The SD-Card debug may not be fully featured, yet, but it has gotten me
to where I can talk to the card.) |
dgisselq |
2919d 11h |
/xulalx25soc/trunk/bench/ |
| 47 |
Fixes the "NAN" clocks/second output, as well as making input timing come closer
to a realistic timing. (I actually don't know what timing the JTAG port is
providing, but ... the new timer is closer.) |
dgisselq |
2997d 15h |
/xulalx25soc/trunk/bench/ |
| 37 |
These fixes were necessary to get the SDRAM into a working simulation
capability. It is finally what it was supposed to be: cycle accurate. Sadly,
to do this, I did need to make a subtle change to rtl/wbsdram.v. (I was having
a problem with external input clocking in Verilator. This fixes it--but its
a Verilator only change--to rtl/wbsdram.v that is.) |
dgisselq |
3005d 15h |
/xulalx25soc/trunk/bench/ |
| 36 |
A linker script, appropriate to the XuLA25-LX25 SoC. |
dgisselq |
3005d 16h |
/xulalx25soc/trunk/bench/ |
| 35 |
Updates the memory testing program to work successfully with the Gnu build
tools--particularly the GNU C-preprocessor from GCC and the GNU assembler from
Binutils. |
dgisselq |
3005d 16h |
/xulalx25soc/trunk/bench/ |
| 31 |
A bug fix, although one that rearranges the bus. The first four I/O locations
have been adjusted. The new locations are reflected in wishbone.html. In
addition, the PWM and UART devices no longer create bus errors when accessed.
Finally, this version uses a `define XULA25 to determine whether or not to build
for the XuLA2-LX9 or the XuLA2-LX25. If defined, it will build for the
XuLA2-LX25. If not, for the XuLA2-LX9. The ideal location for this define
would be to place it into your Xilinx configuration, should you wish to build
for the LX25. |
dgisselq |
3009d 13h |
/xulalx25soc/trunk/bench/ |
| 16 |
Updates to allow a test of the ICAP configuration interface. |
dgisselq |
3075d 14h |
/xulalx25soc/trunk/bench/ |
| 15 |
WORKING VERSION! ... or, at least the memory test works. |
dgisselq |
3077d 10h |
/xulalx25soc/trunk/bench/ |
| 10 |
Changed the name of the memtest.s file. |
dgisselq |
3077d 12h |
/xulalx25soc/trunk/bench/ |
| 4 |
Here's an initial, albeit incomplete, build. |
dgisselq |
3080d 09h |
/xulalx25soc/trunk/bench/ |
