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Subversion Repositories c16

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Rev	Log message	Author	Age	Path
24	no message	jsauermann	6783d 18h	/
23	Fixed problem with wishbone wait-states	jsauermann	6923d 17h	/
22	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'.		6923d 22h	/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6923d 22h	/
20	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'.		7119d 19h	/
19	FPGA Pin desription added.	jsauermann	7119d 19h	/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7420d 18h	/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7420d 18h	/
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7420d 18h	/
15	sample ucf file	jsauermann	7459d 21h	/
14	no message	jsauermann	7467d 22h	/
13	bug in print_unsigned() fixed. Now done as in rtos.c	jsauermann	7510d 16h	/
12	Todo removed	jsauermann	7539d 14h	/
11	First Version	jsauermann	7539d 14h	/
10	Set top of stack of idle task to end of internal memory rather than end of external memory (causing incorrect display of 100 % CPU load).	jsauermann	7539d 15h	/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7539d 15h	/
8	Initialization of compound auto variables added (was TODO)	jsauermann	7546d 18h	/
7	Handle auto variable declarations in compound statements properly	jsauermann	7547d 18h	/
6	New Target polled for testing compiler without the need to simulate interrupts	jsauermann	7547d 18h	/
5	Initial version	jsauermann	7548d 15h	/

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Subversion Repositories c16

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