URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] - Rev 28

Rev	Log message	Author	Age	Path
28	Added old uploaded documents to new repository.	root	5575d 08h	/
27	Added old uploaded documents to new repository.	root	5576d 01h	/
26	New directory structure.	root	5576d 01h	/
25	XOR bug fixed	jsauermann	6634d 08h	/
24	no message	jsauermann	6795d 06h	/
23	Fixed problem with wishbone wait-states	jsauermann	6935d 05h	/
22	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_7'.		6935d 10h	/
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6935d 10h	/
20	This commit was manufactured by cvs2svn to create tag 'Rev_XLNX_5'.		7131d 07h	/
19	FPGA Pin desription added.	jsauermann	7131d 07h	/
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7432d 06h	/
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7432d 06h	/
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7432d 06h	/
15	sample ucf file	jsauermann	7471d 09h	/
14	no message	jsauermann	7479d 10h	/
13	bug in print_unsigned() fixed. Now done as in rtos.c	jsauermann	7522d 04h	/
12	Todo removed	jsauermann	7551d 02h	/
11	First Version	jsauermann	7551d 02h	/
10	Set top of stack of idle task to end of internal memory rather than end of external memory (causing incorrect display of 100 % CPU load).	jsauermann	7551d 03h	/
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7551d 03h	/