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Rev Log message Author Age Path
48 linus 5536d 22h /
47 linus 5536d 22h /
46 linus 5536d 22h /
45 linus 5536d 22h /
44 more on directory structure markom 7631d 16h /
43 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7921d 00h /
42 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7921d 00h /
41 Changed synthesizeable FPGA memory implementation.
Fixed some issues with Xilinx BlockRAM
rherveille 7921d 00h /
40 Updated PDF. lampret 7965d 02h /
39 Added Richard's feedback. lampret 7967d 03h /
38 Undeleted mohor 7987d 16h /
37 no message bbeaver 8223d 23h /
36 minor changes: unified with all common rams samg 8244d 07h /
35 corrected output: output not valid if ce low samg 8244d 12h /
34 added valid checks to behvioral model samg 8244d 13h /
33 added checks and task in behavioral section samg 8245d 14h /
32 no message bbeaver 8246d 19h /
31 no message bbeaver 8250d 20h /
30 no message bbeaver 8251d 19h /
29 got timing checks mostly correct
No functional stuff yet
bbeaver 8251d 19h /

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