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23 Added "beta" section to separate upcoming beta versions or release candidates from released versions.
The currently released version moved to "released".
The upcoming v2.00rc loaded into "beta" is a major release candidate containing performance improvements.
fmax is now typical from 110 MHz to 180 MHz even for low/middle cost FPGA devices. High end FPGA devices allow clock rates over 250 MHz now.
After many cycle count issues caused by description errors in original vendor documents, the v2.00rc testing processes (in progress) rely on the WDC 65C02 documentation and physical chips for reference now.		 fpga_is_funny 2067d 03h /
22 v1.52 PRODUCTION
RESET generates SYNC now, 1 dead cycle delayed		 fpga_is_funny 2101d 07h /
21 fpga_is_funny 2102d 04h /
20 fpga_is_funny 2102d 04h /
19 fpga_is_funny 3966d 09h /
18 RELEASE CANDIDATE V1.5 RC of r65c02_tc.
Major Bug Fixes are available.
Look at the header of r65c02_tc.vhd to get more details.
Because of translation errors made by a third party conversion tool in the past, Verilog sources are no longer available. May be re-activated in the future.

The upcoming PRODUCTION version will be include some enhancements for speed and resource utilization.		 fpga_is_funny 3966d 10h /
17 Added old uploaded documents to new repository. root 5572d 05h /
16 Added old uploaded documents to new repository. root 5572d 21h /
15 New directory structure. root 5572d 21h /
14 Obsolete file fpga_is_funny 5576d 18h /
13 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)		 fpga_is_funny 5584d 23h /
12 - CORRECT "RTI" (wrong: use of stack pointer)
- CORRECT "RMBx" & "SMBx" (wrong: bit translation)
- RENAME all states of "FSM Execution Unit" for better reading
- (85%) Finish working for Specification of cpu65C02_tc
- CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles instead of 7)
- OPTIMIZE end states of "STA" (s197,s207,s200,s213)		 fpga_is_funny 5584d 23h /
11 no message fpga_is_funny 5636d 18h /
10 no message fpga_is_funny 5636d 18h /
9 no message fpga_is_funny 5636d 18h /
8 no message fpga_is_funny 5636d 18h /
7 - Delete unused nets and blocks (same as R6502_TC)
- Rename blocks
- Re-arrage FSM symbols in block FSM_Execution_Unit		 fpga_is_funny 5636d 19h /
6 This commit was manufactured by cvs2svn to create tag 'arelease'. 5671d 00h /
5 This commit was generated by cvs2svn to compensate for changes in r4, which
included commits to RCS files with non-trunk default branches.		 fpga_is_funny 5671d 00h /
4 no message fpga_is_funny 5671d 00h /

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