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72 This commit was manufactured by cvs2svn to create tag 'rel_9'. 7543d 12h /
71 Mbist support added. simons 7543d 12h /
70 A pdf copy of existing doc document. simons 7550d 14h /
69 WBCNTL added, multiple CPU support described. simons 7571d 03h /
68 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7576d 08h /
67 Lower two address lines must be always zero. simons 7576d 08h /
66 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7577d 07h /
65 WB_CNTL register added, some syncronization fixes. simons 7577d 07h /
64 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7597d 08h /
63 Three more chains added for cpu debug access. simons 7597d 08h /
62 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7625d 08h /
61 Lapsus fixed. simons 7625d 08h /
60 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7625d 08h /
59 Reset value for riscsel register set to 1. simons 7625d 08h /
58 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7625d 09h /
57 Multiple cpu support added. simons 7625d 09h /
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 7892d 06h /
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.
mohor 7892d 06h /
54 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7892d 07h /
53 Trst active high. Inverted on higher layer. mohor 7892d 07h /

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