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23 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_8'. 5564d 19h /
22 project released under LGPL mikel262 5564d 19h /
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5564d 20h /
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5564d 20h /
19 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_6'. 6589d 17h /
18 Minor fixes. This release is FPGA proven. mikel262 6589d 17h /
17 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_5'. 6611d 13h /
16 Documentation update, minor fixes mikel262 6611d 13h /
15 Redesigned. Fully pipelined, always ready for data design mikel262 6611d 14h /
14 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_4'. 6615d 13h /
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6615d 13h /
12 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_3'. 6616d 13h /
11 changed ROM memory model to synchronous mikel262 6616d 13h /
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6617d 15h /
9 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_2'. 6620d 02h /
8 Updated DOC mikel262 6620d 02h /
7 documentation update. minor area optimization. mikel262 6620d 12h /
6 minor updates mikel262 6621d 12h /
5 This commit was manufactured by cvs2svn to create tag 'MDCT_REL_B1_1'. 6621d 14h /
4 area optimization - 100 slices less mikel262 6621d 14h /

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