OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] - Rev 461

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
461 Updated to be much stricter about usage. jeremybennett 4906d 13h /
460 Merged in changes from Jeremy to Ethernet, updated documentation of tests, added l.nop 8 and l.nop 9 opcodes to turn tracing on and off. Updated documentation to cover l.nop opcodes. jeremybennett 4906d 15h /
459 Add option to bld-all.sh to explicitly set control load of make, and fix typos. julius 4906d 21h /
458 or1ksim testsuite updates julius 4907d 19h /
457 or1ksim - couple of ethernet peripheral updates, fixup of ethernet regression test so all tests pass again. julius 4916d 09h /
456 ORPSoCv2 or1200 - SPRs module format and comment update. Or1200 monitor Verilog now displays report and exit l.nops to stdout by default. julius 4916d 11h /
455 Updated to support threads. Does require thread debugging enabled in uClibc. jeremybennett 4920d 13h /
454 Updated to incorporate pthreads for Linux tool chain. jeremybennett 4922d 14h /
453 Updates to support constructor/destructor initialization for uClibc. jeremybennett 4923d 01h /
452 Update to define __UCLIBC__ when using the uClibc tool chain. jeremybennett 4923d 09h /
451 More tidying up. jeremybennett 4927d 05h /
450 Simplified (and hopefully more reliable) Ethernet MAC/PHY. jeremybennett 4927d 09h /
449 ORPSoC - or1200_monitor.v additions enabling new experimental execution checks.

Replace use of "clean-all" with "distclean" as make rule to clean things.
julius 4929d 06h /
448 Changed or32 to openrisc as Linux architecture name. jeremybennett 4929d 16h /
447 Updates to register order. jeremybennett 4930d 10h /
446 gdb-7.2 gdbserver updates. julius 4931d 04h /
445 gdbserver update to use kernel port ptrace register definitions. julius 4932d 01h /
444 Changes to ABI handling of varargs. jeremybennett 4932d 10h /
443 Work in progress on more efficient Ethernet. jeremybennett 4932d 13h /
442 OR1Ksim - adding trace controlability by SIGUSR1 signal. julius 4933d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.