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Subversion Repositories openrisc

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Rev	Log message	Author	Age	Path
82	Major restructuring of the testbench, now named testsuite to bring it into the main package with its own configuration. Uses DejaGNU and builds using a standard top level "make check". Incorporate Mark Jarvis's fixes for Mac OS X.	jeremybennett	5172d 12h	/
81	Directory no longer used.	jeremybennett	5172d 12h	/
80	Add missing configuration files to SVN.	jeremybennett	5172d 15h	/
79	Fixed retry loop in or_debug_proxy, hopefully more stable when physically resetting the board	julius	5184d 16h	/
78	Fixed typo in Silos workaround script	rherveille	5185d 11h	/
77	Added support for Silvaco's Silos simulator Added workaround for Silos's exit code behaviour	rherveille	5185d 12h	/
76	Added: +libext+.v Added: +incdir+.	rherveille	5186d 11h	/
75	Fixed toolchain script's cygwin ncurses check	julius	5191d 14h	/
74	Toolchain script fix for ncurses header checking	julius	5209d 16h	/
73	toolchain script error fix	julius	5209d 17h	/
72	Toolchain install script: or1ksim location changed, few tweaks	julius	5212d 14h	/
71	ORPSoC board builds, adding readmes	julius	5228d 21h	/
70	ORPSoC cycle accurate trace generation now compatible with latest version of Verilator \(3.800\) - This will break VCD generation on systems which earlier verilator versions\!	julius	5233d 02h	/
69	ORPSoC xilinx ml501 board update - added ethernet eupport and software test	julius	5233d 03h	/
68	Fixed up a couple of Makefile things in ORPSoCv2	julius	5235d 18h	/
67	New synthesizable builds of ORPSoC - first for the Xilinx ML501 Virtex 5 board, with working Xilinx MIG DDR2 Controller - added new pad option to bin2vmem, moved spi controller from or1k_startup module to its own directory	julius	5235d 21h	/
66	Fixed the simulator-assisted printf l.nop in cycle accurate, and supporting software.	julius	5255d 19h	/
65	ORPSoCv2 update: or1200_defines DVRDCR value, verilog testbench uart decoder fix	julius	5260d 01h	/
64	Trying to fix the system c model jtagsc.h checkout problem, also removed dependency generation in the system c modules makefile.	julius	5262d 20h	/
63	Finally adding RSP server to cycle accurate model, based on work by Jeremey Bennett but slightly modified for the debug unit we use. Adding binary logging file mode to cycle accurate model which allows smaller and quicker execution logging, along with binary log reader in sw/utils. Adding cycle accurate wishbone bus transaction log generation. still some bugs in CA model for some reason where it skips cycles when logging either execution or bus transactions. Changing or1200 du allowing hardware watchpoints on data load and stores.	julius	5272d 18h	/

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Subversion Repositories openrisc

[/] - Rev 82

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