URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] - Rev 31

Rev	Log message	Author	Age	Path
31	accurate source code copyright comment header	homer.xing	4479d 00h	/
30	LGPL header	homer.xing	4489d 03h	/
29	default net type is wire	homer.xing	4496d 00h	/
28	Non-net port XXX cannot be of mode input, when using the "`default_nettype none" to turn off automatic inference of wires in the design. ha ha	homer.xing	4496d 03h	/
27	definition for undefined wire	homer.xing	4496d 03h	/
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4501d 23h	/
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4502d 00h	/
24	LGPL claim in each source hdl file	homer.xing	4510d 00h	/
23	LGPL license text	homer.xing	4510d 00h	/
22	Change TAB to space	homer.xing	4510d 01h	/
21	Add detailed input data capture condition in the document	homer.xing	4510d 02h	/
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4511d 04h	/
19	Update synthesis result	homer.xing	4511d 21h	/
18	add synthesis result	homer.xing	4511d 21h	/
17	use logic for $f3m_mux6$	homer.xing	4511d 23h	/
16	Add synthesis configuration files	homer.xing	4512d 02h	/
15	add document. ha ha ha	homer.xing	4512d 03h	/
14	Move constraint file	homer.xing	4512d 04h	/
13	Add document and synthesis directories	homer.xing	4512d 04h	/
12	Simplify the interface of the core.	homer.xing	4512d 05h	/