URL https://opencores.org/ocsvn/rio/rio/trunk

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Rev	Log message	Author	Age	Path
30	Changing name tags/1.0.1 to tags/1.0.1-release.	magro732	3569d 19h	/
29	Fixed bug in RioSwitch internal Wishbone interconnects.	magro732	3569d 20h	/
28	Correcting bug in RioSwitch.vhd internal Wishbone interconnect. Modifying an existing test case in TestRioSwitch.vhd to provoke the error.	magro732	3569d 21h	/
27	Adding missing code to single-symbol pipelined transmitter. Not tested nor copiled.	magro732	3571d 08h	/
26	Temporary checkin of parallelSymbols branch. It does not work yet.	magro732	3731d 20h	/
25	Correcting compiler errors in TestRioPcsUart.vhd	magro732	3738d 13h	/
24	Changing errornous use statement.	magro732	3738d 14h	/
23	Tagging alpha release 2.0.0.	magro732	3855d 07h	/
22	Tagging release 1.0.0.	magro732	3855d 07h	/
21	Branching of a single symbol version of the new RioSerial.	magro732	3855d 07h	/
20	Adding software C-stack and matching VHDL modules.	magro732	3920d 10h	/
19	Removing synthesis warnings.	magro732	3945d 09h	/
18	Making RioSerial entity the same as before+minor fixes.	magro732	3946d 08h	/
17	Removing latch and improving timing.	magro732	3947d 08h	/
16	Removed FIFO between RioSerial and PCS. Transmitter works without idle ticks. Internal symbol fifo increased. Changed readContentEnd_o timing.	magro732	3947d 09h	/
15	All testcases are ok. Still needs some tweeks though.	magro732	3951d 10h	/
14	Most issues solved, testbench issues remains.	magro732	3954d 09h	/
13	Timeouts are working.	magro732	3957d 10h	/
12	Backup of recent work, debugging new RioSerial.	magro732	3968d 08h	/
11	Receiver ready, transmitter is compiling.	magro732	3968d 09h	/

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