URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 151

Rev	Log message	Author	Age	Path
151	Started to include generic VHDL description of memories.	jlechner	5217d 00h	/
150	Added old uploaded documents to new repository.	root	5553d 05h	/
149	Added old uploaded documents to new repository.	root	5553d 11h	/
148	New directory structure.	root	5553d 11h	/
147	- Updated to use current example.	cwalter	6327d 19h	/
146	- Changed to compile UART example.	cwalter	6327d 21h	/
145	- Added more VHDL files to project.	cwalter	6327d 21h	/
144	- IF stage now uses autogenerated VHDL files.	cwalter	6327d 21h	/
143	- Added more complex UART example.	cwalter	6327d 21h	/
142	- Added gap between characters sent and changed last character to CR.	cwalter	6327d 21h	/
141	- Added delay between characters.	cwalter	6327d 22h	/
140	- Test bench for RISE with UART.	cwalter	6327d 22h	/
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6327d 22h	/
138	- Fixed binary to VHDL converter.	cwalter	6327d 23h	/
137	- Added binary to VHDL converter.	cwalter	6327d 23h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6327d 23h	/
135	uart_address_0 was a latch -> changed	ustadler	6328d 19h	/
134	Added second test program for testing uart.	jlechner	6328d 19h	/
133	- Fixed bug with ST opcodes.	cwalter	6328d 21h	/
132	Added test program for testing uart.	jlechner	6328d 21h	/