OpenCores
URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] - Rev 26

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
26 This commit was manufactured by cvs2svn to create tag 'rel_8'. 7390d 00h /
25 CTRL register bit fields changed, VATS testing support added. simons 7390d 00h /
24 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7641d 02h /
23 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7641d 02h /
22 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7641d 02h /
21 Byte selects changed. simons 7641d 02h /
20 This commit was manufactured by cvs2svn to create tag 'rel_6'. 7642d 06h /
19 Errors fixed. simons 7642d 06h /
18 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7645d 03h /
17 Define mess fixed. simons 7645d 03h /
16 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7645d 07h /
15 Defines set in order. simons 7645d 07h /
14 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7646d 00h /
13 8-bit WB access enabled. simons 7646d 00h /
12 Error fixed. simons 7666d 07h /
11 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7684d 07h /
10 Slave select signal generation bug fixed, default case added when reading registers, to avoid latches. simons 7684d 07h /
9 Support for 128 bits character length added. Zero value divider bug fixed. simons 7725d 00h /
8 Automatic slave select signal generation added. simons 7745d 02h /
7 Support for 64 bit caharacter len added. simons 7833d 14h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.