URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

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Rev	Log message	Author	Age	Path
113	Timescale was unified.	gabrieloshiro	5554d 06h	/
112	Created a global timescale file for the project.	creep	5554d 06h	/
111	Performed some linting after coding was finished.	creep	5554d 21h	/
110	All addressing modes and special instructions have been coded and simulated. The file still requires coments, linting and some coverage.	creep	5554d 22h	/
109	PLA and PLP are coded and simulated.	creep	5555d 01h	/
108	PHA and PHP are coded and simulated.	creep	5555d 02h	/
107	The RTS instruction is working fine. Coded and simulated.	creep	5555d 03h	/
106	First stable version. Things seems to be working. Simulation is currently at 20%.	gabrieloshiro	5555d 03h	/
105	The RTI instruction is working fine. Coded and simulated.	creep	5555d 03h	/
104	The BRK instruction is working. The reset vector was tested also.	creep	5555d 05h	/
103	Some early modifications to support the special stack instructions.	creep	5555d 22h	/
102	Some early modifications to support the special stack instructions.	creep	5556d 01h	/
101	Absolute indirect addressing mode is coded and simulated.	creep	5556d 05h	/
100	IDY WRITE TYPE instructions are coded and simulated.	creep	5556d 06h	/
99	Only Package.v should be used.	creep	5556d 06h	/
98	Updated status and some comments.	creep	5556d 06h	/
97	Removed obsolete TODO.	creep	5556d 06h	/
96	IDY READ TYPE instructions are coded and simulated. IDY WRITE TYPE instructions are coded but still requires simulation.	creep	5558d 22h	/
95	IDX addressing mode is also 100%, coded and simulated.	creep	5559d 02h	/
94	Relative addressing mode is almost 100% functional. It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.	creep	5559d 22h	/

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Subversion Repositories t6507lp

[/] - Rev 113

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