URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

[/] - Rev 84

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Rev	Log message	Author	Age	Path
84	New directory structure.	root	5570d 12h	/
83	Some fixes from Guy-- replace case with casex.	hharte	5643d 18h	/
82	Clean up spacing	hharte	5653d 14h	/
81	Initial version of TV80 Wishbone Wrapper	hharte	5653d 15h	/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6753d 03h	/
79	Added JR self-checking test	ghutchis	6753d 03h	/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6796d 04h	/
77	Added back files lost after server crash	ghutchis	6827d 22h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6907d 04h	/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	6907d 04h	/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6907d 05h	/
73	Added RC4 encrypt/decrypt test	ghutchis	6919d 00h	/
72	Added copyright header	ghutchis	6919d 00h	/
71	Ported UART from T80	ghutchis	6980d 04h	/
70	Added test for T16450 UART	ghutchis	7030d 23h	/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7030d 23h	/
68	Updated nwtest to reflect changes in register interface to simple_gmii. In particular, interrupt bits for packet arrival and sending now need to be explicitly cleared afterwards.	ghutchis	7039d 00h	/
67	Updated register generator based on testing with simple_gmii. Changed how interrupt output mux is created, fixed many bugs.	ghutchis	7039d 00h	/
66	Modified top level testbench to reflect changes in simple_gmii block	ghutchis	7039d 00h	/
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7039d 00h	/

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Subversion Repositories tv80

[/] - Rev 84

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