URL https://opencores.org/ocsvn/uart16750/uart16750/trunk

Subversion Repositories uart16750

[/] - Rev 25

Rev	Log message	Author	Age	Path
25	UART16750: Updated testbench	hasw	5052d 00h	/
24	Inverted low active outputs when RST is active	hasw	5052d 00h	/
23	Fixed paths in Makefile for simulation	hasw	5416d 03h	/
22	Removed old stimuli data file, created by perl script	hasw	5416d 03h	/
21	Updated simulation files	hasw	5416d 03h	/
20	UART16750: Check only half of the stop bit in the receiver to resume faster to the IDLE state	hasw	5546d 02h	/
19	Added old uploaded documents to new repository.	root	5562d 06h	/
18	Added old uploaded documents to new repository.	root	5562d 11h	/
17	New directory structure.	root	5562d 11h	/
16	UART16750: Added example project	hasw	5582d 23h	/
15	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5592d 01h	/
14	UART16750: Decreased input filter size. De-assert IIR FIFO64 when FIFO is disabled. Fixed typo. Added FIFO 64 tests.	hasw	5593d 03h	/
13	UART16750: Added automatic flow control	hasw	5606d 04h	/
12	UART16750: Updated stimuli script with automatic flow control tests	hasw	5606d 04h	/
11	UART16750: Removed dependency from std_logic_unsigned	hasw	5606d 04h	/
10	UART16750: Removed dependency from std_logic_unsigned	hasw	5606d 04h	/
9	Registered control line outputs	hasw	5615d 06h	/
8	Make memory read in generic FIFO model synchronous for optimized used with XST	hasw	5615d 06h	/
7	Removed async. reset of FIFO memory cells for optimized usage of default FIFO model with XST	hasw	5616d 10h	/
6	THR empty interrupt register connected to RST	hasw	5616d 11h	/