URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [bench/] [verilog/] [oc8051_tb.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5513d 21h	/8051/trunk/bench/verilog/oc8051_tb.v
185		root	5569d 22h	/8051/trunk/bench/verilog/oc8051_tb.v
167	add readmem for ea.	simont	7674d 02h	/8051/trunk/bench/verilog/oc8051_tb.v
166	Change test monitor from ports to external data memory.	simont	7674d 19h	/8051/trunk/bench/verilog/oc8051_tb.v
165	remove dumpvars.	simont	7674d 23h	/8051/trunk/bench/verilog/oc8051_tb.v
156	add FREQ paremeter.	simont	7675d 01h	/8051/trunk/bench/verilog/oc8051_tb.v
124	add support for external rom from xilinx ramb4	simont	7725d 02h	/8051/trunk/bench/verilog/oc8051_tb.v
120	defines for pherypherals added	simont	7731d 00h	/8051/trunk/bench/verilog/oc8051_tb.v
111	Remove instruction cache and wb_interface	simont	7737d 17h	/8051/trunk/bench/verilog/oc8051_tb.v
103	rename signals	simont	7738d 21h	/8051/trunk/bench/verilog/oc8051_tb.v
84	remove wb_bus_mon	simont	7817d 22h	/8051/trunk/bench/verilog/oc8051_tb.v
74	add module oc8051_wb_iinterface	simont	7894d 20h	/8051/trunk/bench/verilog/oc8051_tb.v
68	add instruction cache and DELAY parameters for external ram, rom	simont	7898d 23h	/8051/trunk/bench/verilog/oc8051_tb.v
59	add external rom	simont	7905d 17h	/8051/trunk/bench/verilog/oc8051_tb.v
46	prepared header	simont	7922d 19h	/8051/trunk/bench/verilog/oc8051_tb.v
37	added signals ack, stb and cyc	simont	7949d 21h	/8051/trunk/bench/verilog/oc8051_tb.v
4	Code repaired to satisfy the linter; testbech fails	markom	7970d 01h	/8051/trunk/bench/verilog/oc8051_tb.v
2	Initial CVS import	simont	7985d 23h	/8051/trunk/bench/verilog/oc8051_tb.v