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[/] [openarty/] [trunk/] [rtl/] [fasttop.v] - Rev 24

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24 Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board.
dgisselq 2846d 02h /openarty/trunk/rtl/fasttop.v
13 Here are the updates necessary to get the initial Quad SPI flash driver working.
This includes in particular the bus interconnect (in fastmaster.v), and the
final hookup to the external wires (in fasttop.v).
dgisselq 2858d 02h /openarty/trunk/rtl/fasttop.v
12 A work in progress. This checkin contains fixes for the flash (mostly),
together with some logic reductions facilitating full speed (200MHz) build.
dgisselq 2859d 05h /openarty/trunk/rtl/fasttop.v
3 Initial set of files. The flash appears to work, memory hasn't been started,
the MDIO controller works in simulation, etc. Everything below fasttop.v works
at 200MHz (not the CPU---yet).
dgisselq 2874d 09h /openarty/trunk/rtl/fasttop.v

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