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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [bin/] [asm2ihex.sh] - Rev 200

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200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3419d 06h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4410d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4454d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4761d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
73 Update all bash scripts headers with "#!/bin/bash" instead of "#!/bin/sh".
This will prevent compatibility problems in systems where bash isn't the default shell.		 olivier.girard 5051d 09h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5268d 10h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
17 Updated header with SVN info olivier.girard 5415d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5450d 07h /openmsp430/trunk/core/sim/rtl_sim/bin/asm2ihex.sh

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