OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [or1200/] [doc/] [openrisc1200_supplementary_prm.odt] - Rev 431

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
431 Updated and move OR1200 supplementary manual.

or_debug_proxy GDB RSP interface fix.

ORPSoC S/W and makefile updates.		 julius 4939d 01h /openrisc/trunk/or1200/doc/openrisc1200_supplementary_prm.odt
353 OR1200 RTL and ORPSoCv2 update, fixing Verilator build capability.
* or1200/rtl/verilog/or1200_sprs.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_sprs.v: ""
* or1200/rtl/verilog/or1200_ctrl.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_ctrl.v: ""
* or1200/rtl/verilog/or1200_except.v: Verilator public and access comments
* orpsocv2/rtl/verilog/components/or1200/or1200_except.v: ""
* orpsocv2/rtl/verilog/components/wb_ram_b3/wb_ram_b3.v: Some
Verilator related Lint issues fixed.

ORPSoCv2: Removed bus arbiter snooping functions from OrpsocAccess and
updated RAM model hooks for new RAM.
* orpsocv2/bench/sysc/include/Or1200MonitorSC.h: Remove arbiter snooping
* orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp: ""
* orpsocv2/bench/sysc/include/OrpsocAccess.h: Remove arbiter snooping,
change include and classes for new RAM model.
* orpsocv2/bench/sysc/src/OrpsocAccess.cpp: ""

or_debug_proxy - fixing sleep and Windows make issues:
* or_debug_proxy/src/gdb.c: Removed all sleep - still to be fixed properly
* or_debug_proxy/Makefile: Remove VPI file when building on Cygwin (deprecated)

ORPmon play around, various changes to low level files.		 julius 5015d 01h /openrisc/trunk/docs/openrisc1200_supplementary_prm.odt
257 Changed or1200 supplementary manual from referring or or1200v2 to be just for the or1200 in general julius 5024d 04h /openrisc/trunk/docs/openrisc1200_supplementary_prm.odt
191 Updated to clarify use of r9 in the l.jalr delay slot. jeremybennett 5071d 23h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
129 Previous commit was before saving file. jeremybennett 5099d 02h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
125 Update to specification of l.xori. jeremybennett 5099d 10h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
120 Documents exception generation by l.jalr and l.jr jeremybennett 5100d 23h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
119 Updated to clarify exceptions for division and details of multiplication. jeremybennett 5101d 11h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
117 Updates on l.ff1, l.fl1 and l.maci. jeremybennett 5103d 23h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
113 Updates to exception handling for l.add and l.div jeremybennett 5105d 23h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
108 Updated to clarify overflow and exceptions for l.add, l.addc, l.addi, l.addic, l.div and l.divu. jeremybennett 5108d 22h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
103 Updated to clarify lf.madd.d and lf.madd.s opcodes. jeremybennett 5113d 03h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt
92 Initial version of documents to capture additional information, particularly about the OpenRISC 1200 version 2. jeremybennett 5149d 00h /openrisc/trunk/docs/openrisc1200v2_supplementary_prm.odt

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.