URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [sw/] [tests/] [or1200/] [sim/] [or1200-ffl1.S] - Rev 807

Rev	Log message	Author	Age	Path
499	ORPSoC OR1200 updates - added l.ext instructions with tests, ammended some MAC bugs, decode stage cleanup	julius	4840d 06h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S
425	ORPSoC update: GDB servers in VPI and System C model updated to deal with packets gdb-7.2 sends. Documentation updated. Reference design tests can now be run in or1ksim (added rule to sim/bin/Makefile). or1200-except doesn't appear to work as illegal instruction error isn't causing jump to vector. Updated Or1200 tests to report test success value and then exit with value 0.	julius	4953d 04h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S
403	ORPSoC big upgrade - intermediate check in. Lots still missing. To come very shortly.	julius	4968d 09h	/openrisc/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S