URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] [sdhc-sc-core/] [trunk/] [sim/] [sim.tcl] - Rev 185

Rev	Log message	Author	Age	Path
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	4901d 10h	/sdhc-sc-core/trunk/sim/sim.tcl
170	License rewritten to BSD	rkastl	4904d 03h	/sdhc-sc-core/trunk/src/sim/sim.tcl
164	Headers updated (LGPL, consistent format)	rkastl	4904d 03h	/sdhc-sc-core/trunk/src/sim/sim.tcl
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4904d 04h	/sdhc-sc-core/trunk/src/sim/sim.tcl
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4904d 04h	/sdhc-sc-core/trunk/src/sim/sim.tcl
128	Sim: Support for psl files added.	rkastl	4904d 04h	/sdhc-sc-core/trunk/src/sim/sim.tcl
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4904d 04h	/sdhc-sc-core/trunk/src/sim/sim.tcl
120	SdWbSlave: ClassicRead and ClassicWrite work	rkastl	4904d 07h	/sdhc-sc-core/trunk/src/sim/sim.tcl
106	Fixes #29: All cards respond, but they do not all work.	rkastl	4904d 07h	/sdhc-sc-core/trunk/src/sim/sim.tcl
86	Rs232Tx: testbench, refs #28	rkastl	4904d 07h	/sdhc-sc-core/trunk/src/sim/sim.tcl
85	Synthese: TbdSd refactored to enable sharing. Sim: SdVerificationTestbench to new tcl script ported SdController: TimeoutGenerator added, refs #27	rkastl	4904d 07h	/sdhc-sc-core/trunk/src/sim/sim.tcl
79	Rs232Tx: added to TbdSd TimeoutGenerator: written	rkastl	4904d 07h	/sdhc-sc-core/trunk/src/sim/sim.tcl