URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_top.v] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5570d 13h	/spi/trunk/rtl/verilog/spi_top.v
21	Byte selects changed.	simons	7642d 07h	/spi/trunk/rtl/verilog/spi_top.v
15	Defines set in order.	simons	7646d 12h	/spi/trunk/rtl/verilog/spi_top.v
13	8-bit WB access enabled.	simons	7647d 05h	/spi/trunk/rtl/verilog/spi_top.v
10	Slave select signal generation bug fixed, default case added when reading registers, to avoid latches.	simons	7685d 12h	/spi/trunk/rtl/verilog/spi_top.v
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7726d 05h	/spi/trunk/rtl/verilog/spi_top.v
8	Automatic slave select signal generation added.	simons	7746d 07h	/spi/trunk/rtl/verilog/spi_top.v
7	Support for 64 bit caharacter len added.	simons	7834d 19h	/spi/trunk/rtl/verilog/spi_top.v
2	Initial import	simons	8033d 07h	/spi/trunk/rtl/verilog/spi_top.v