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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] [uart_defines.v] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5573d 07h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8149d 00h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
75 Endian define added. Big Byte Endian is selected by default. mohor 8149d 00h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
53 Scratch register define added. mohor 8219d 08h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8226d 20h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8233d 20h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8327d 20h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 01h /uart16550/tags/asyst_3/rtl/verilog/uart_defines.v

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