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[/] [uart16550/] [tags/] [asyst_3/] [rtl/] [verilog/] [uart_fifo.v] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5573d 07h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
77 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 8149d 00h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
71 Removed confusing comment gorban 8185d 20h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
66 rx push changed to be only one cycle wide. mohor 8210d 03h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
62 Bug that was entered in the last update fixed (rx state machine). mohor 8212d 08h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8213d 02h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8233d 19h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8252d 02h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8252d 23h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
33 Small synopsis fixes gorban 8271d 07h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8327d 20h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
28 FIFO was not cleared after the data was read bug fixed. mohor 8328d 08h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 01h /uart16550/tags/asyst_3/rtl/verilog/uart_fifo.v

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