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[/] [uart16550/] [tags/] [rel_1/] [rtl/] [verilog/] [uart_fifo.v] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5563d 17h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8139d 10h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
71 Removed confusing comment gorban 8176d 07h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
66 rx push changed to be only one cycle wide. mohor 8200d 13h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
62 Bug that was entered in the last update fixed (rx state machine). mohor 8202d 18h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8203d 12h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8224d 05h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8242d 12h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8243d 09h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
33 Small synopsis fixes gorban 8261d 17h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8318d 06h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
28 FIFO was not cleared after the data was read bug fixed. mohor 8318d 18h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8319d 11h /uart16550/tags/rel_1/rtl/verilog/uart_fifo.v

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