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[/] [uart16550/] [tags/] [rel_1/] [rtl/] [verilog/] [uart_receiver.v] - Rev 106

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106 New directory structure. root 5574d 00h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8149d 17h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8200d 13h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
67 Missing declaration of rf_push_q fixed. mohor 8210d 21h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
66 rx push changed to be only one cycle wide. mohor 8210d 21h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
64 Warnings cleared. mohor 8212d 02h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
63 Synplicity was having troubles with the comment. mohor 8212d 02h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8213d 19h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8218d 00h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
51 Igor fixed break condition bugs gorban 8220d 14h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8224d 19h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8227d 12h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8232d 14h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8233d 12h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8234d 12h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
40 Synthesis bugs fixed. Some other minor changes gorban 8250d 21h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8252d 19h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8253d 16h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
35 Fixes to break and timeout conditions gorban 8260d 19h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v
33 Small synopsis fixes gorban 8272d 00h /uart16550/tags/rel_1/rtl/verilog/uart_receiver.v

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