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[/] [uart16550/] [tags/] [rel_1/] [rtl/] [verilog/] [uart_regs.v] - Rev 106

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Rev	Log message	Author	Age	Path
106	New directory structure.	root	5573d 12h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
78	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8149d 05h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
68	lsr[7] was not showing overrun errors.	mohor	8203d 08h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
66	rx push changed to be only one cycle wide.	mohor	8210d 08h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
64	Warnings cleared.	mohor	8211d 14h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
63	Synplicity was having troubles with the comment.	mohor	8211d 14h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8213d 11h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
59	MSR register fixed.	mohor	8216d 08h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
58	After reset modem status register MSR should be reset.	mohor	8216d 12h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
56	thre irq should be cleared only when being source of interrupt.	mohor	8217d 12h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8218d 13h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
52	Scratch register added	gorban	8220d 02h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8224d 07h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8227d 00h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8232d 02h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8234d 00h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
44	fixed more typo bugs	gorban	8248d 00h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
43	lsr1r error fixed.	mohor	8248d 07h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
42	ti_int_pnd error fixed.	mohor	8248d 07h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v
41	ti_int_d error fixed.	mohor	8248d 07h	/uart16550/tags/rel_1/rtl/verilog/uart_regs.v

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Subversion Repositories uart16550

[/] [uart16550/] [tags/] [rel_1/] [rtl/] [verilog/] [uart_regs.v] - Rev 106

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