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[/] [uart16550/] [tags/] [rel_1/] [rtl/] [verilog/] [uart_top.v] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5573d 08h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
78 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8149d 02h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
65 Warnings fixed (unused signals removed). mohor 8211d 10h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8224d 04h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8226d 21h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
37 Heavily rewritten interrupt and LSR subsystems.
Many bugs hopefully squashed.		 gorban 8253d 01h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
33 Small synopsis fixes gorban 8271d 09h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
30 Modified port names again gorban 8327d 03h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8327d 21h /uart16550/tags/rel_1/rtl/verilog/uart_top.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8329d 02h /uart16550/tags/rel_1/rtl/verilog/uart_top.v

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