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[/] [uart16550/] [tags/] [rel_2/] [rtl/] [verilog/] [uart_defines.v] - Rev 106

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Rev Log message Author Age Path
106 New directory structure. root 5563d 15h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
97 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7372d 21h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
89 adjusted comment + define dries 7569d 18h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
87 This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. gorban 7662d 09h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7986d 02h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
75 Endian define added. Big Byte Endian is selected by default. mohor 8139d 08h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
53 Scratch register define added. mohor 8209d 16h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8217d 04h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8224d 04h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
29 Things connected to parity changed.
Clock devider changed.		 mohor 8318d 04h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v
27 Stop bit bug fixed.
Parity bug fixed.
WISHBONE read cycle bug fixed,
OE indicator (Overrun Error) bug fixed.
PE indicator (Parity Error) bug fixed.
Register read bug fixed.		 mohor 8319d 09h /uart16550/tags/rel_2/rtl/verilog/uart_defines.v

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