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[/] [uart16550/] [tags/] [rel_3/] [rtl/] [verilog/] [uart_receiver.v] - Rev 106

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106 New directory structure. root 5563d 17h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
102 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7317d 14h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
100 Repaired bug in receiver. When stop bit is sampled and next clock RX input was '0', state machine stayed locked until next '1' which cause loosing at least start bit in case of larger difference of bit times between 2 UARTs. tadejm 7317d 15h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
84 The uart_defines.v file is included again in sources. gorban 7979d 06h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
79 Bug Fixes:
* Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
Problem reported by Kenny.Tung.
* Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.

Improvements:
* Made FIFO's as general inferrable memory where possible.
So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
This saves about 1/3 of the Slice count and reduces P&R and synthesis times.

* Added optional baudrate output (baud_o).
This is identical to BAUDOUT* signal on 16550 chip.
It outputs 16xbit_clock_rate - the divided clock.
It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.		 gorban 7986d 04h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
69 More than one character was stored in case of break. End of the break
was not detected correctly.		 mohor 8190d 06h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
67 Missing declaration of rf_push_q fixed. mohor 8200d 14h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
66 rx push changed to be only one cycle wide. mohor 8200d 14h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
64 Warnings cleared. mohor 8201d 19h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
63 Synplicity was having troubles with the comment. mohor 8201d 19h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
61 overrun signal was moved to separate block because many sequential lsr
reads were preventing data from being written to rx fifo.
underrun signal was not used and was removed from the project.		 mohor 8203d 12h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
57 timeout irq must be set regardless of the rda irq (rda irq does not reset the
timeout counter).		 mohor 8207d 17h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
51 Igor fixed break condition bugs gorban 8210d 07h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
50 Bug in LSR[0] is fixed.
All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.		 gorban 8214d 12h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
48 Updated specification documentation.
Added full 32-bit data bus interface, now as default.
Address is 5-bit wide in 32-bit data bus mode.
Added wb_sel_i input to the core. It's used in the 32-bit mode.
Added debug interface with two 32-bit read-only registers in 32-bit mode.
Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
My small test bench is modified to work with 32-bit mode.		 gorban 8217d 05h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
47 Fixed: timeout and break didn't pay attention to current data format when counting time gorban 8222d 07h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
46 Fixed bug that prevented synthesis in uart_receiver.v gorban 8223d 05h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
45 Lots of fixes:
Break condition wasn't handled correctly at all.
LSR bits could lose their values.
LSR value after reset was wrong.
Timing of THRE interrupt signal corrected.
LSR bit 0 timing corrected.		 gorban 8224d 05h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
40 Synthesis bugs fixed. Some other minor changes gorban 8240d 14h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v
39 Comments in Slovene language deleted, few small fixes for better work of
old tools. IRQs need to be fix.		 mohor 8242d 12h /uart16550/tags/rel_3/rtl/verilog/uart_receiver.v

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