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[/] [uart16550/] [tags/] [rel_4/] [bench/] [verilog/] [uart_test.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5563d 06h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
104	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7289d 01h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7372d 12h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
86	restored include for uart_defines.v in uart_test.v	gorban	7932d 03h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
83	Reverted to include uart_defines.v file in other files again.	gorban	7978d 19h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8216d 18h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
38	small update to test interrupts	gorban	8242d 22h	/uart16550/tags/rel_4/bench/verilog/uart_test.v
14		gorban	8329d 23h	/uart16550/tags/rel_4/bench/verilog/uart_test.v