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[/] [uart16550/] [tags/] [rel_4/] [bench/] [verilog/] [wb_mast.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5572d 00h	/uart16550/tags/rel_4/bench/verilog/wb_mast.v
104	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7297d 19h	/uart16550/tags/rel_4/bench/verilog/wb_mast.v
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8225d 12h	/uart16550/tags/rel_4/bench/verilog/wb_mast.v