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[/] [uart16550/] [tags/] [rel_4/] [bench/] [verilog/] [wb_model_defines.v] - Rev 106

Rev	Log message	Author	Age	Path
106	New directory structure.	root	5571d 13h	/uart16550/tags/rel_4/bench/verilog/wb_model_defines.v
104	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7297d 08h	/uart16550/tags/rel_4/bench/verilog/wb_model_defines.v
93	Testbench with complete selfchecking. BUG is that THRE status is set at the end of last sent bit when TX FIFO is empty instead when only TX FIFO gets empty. This causes testcases not to finish.	tadejm	7380d 19h	/uart16550/tags/rel_4/bench/verilog/wb_model_defines.v