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[/] [w11/] [tags/] [w11a_V0.6/] [rtl/] [w11a/] [pdp11_tmu.vhd] - Rev 24

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Rev	Log message	Author	Age	Path
24	- major release w11a_V0.60 (tagged)	wfjm	3642d 04h	/w11/tags/w11a_V0.6/rtl/w11a/pdp11_tmu.vhd
17	- interim release w11a_V0.56 (untagged) - re-organized handling of board and derived clocks in test benches - added message filter definitions for some designs (.mfset files) - added Cypress EZ-USB FX2 controller (USB interface) - added firmware for EZ-USB FX2 supporting jtag access and data transfer - FPGA configure over USB now supported directly in make build flow - added test systems for USB testing and rlink over USB verification - no functional change of w11a CPU core or any pre-existing test systems - Note: Carefully read the disclaimer about usage of USB VID/PID numbers in the file README_USB-VID-PID.txt. You'll be responsible for any misuse of the defaults provided with the project sources !!	wfjm	4162d 06h	/w11/tags/w11a_V0.6/rtl/w11a/pdp11_tmu.vhd
13	- interim release w11a_V0.532 (untagged) - re-organize modules 'human I/O' interface on Digilent boards - add test designs for 'human I/O' interface for atlys,nexys2, and s3board - small updates in crc8 and dcm areas - with one exception all vhdl sources use now numeric_std	wfjm	4571d 14h	/w11/tags/w11a_V0.6/rtl/w11a/pdp11_tmu.vhd
8	- interim release w11a_V0.51 (untagged) - migrate to ibus protocol verion 2 - nexys2 systems now with DCM derived system clock supported - sys_w11a_n2 now runs with 58 MHz clksys	wfjm	4929d 04h	/w11/tags/w11a_V0.6/rtl/w11a/pdp11_tmu.vhd
2	initial source upload (no docs yet)	wfjm	5070d 09h	/w11/tags/w11a_V0.6/rtl/w11a/pdp11_tmu.vhd

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