OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] - Rev 186

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
186 root 5494d 16h /
185 root 5550d 18h /
184 initial inport. simont 7615d 22h /
183 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7629d 10h /
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7629d 10h /
181 Simulation reports added. simont 7629d 10h /
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7629d 11h /
179 add /* synopsys xx_case */ to case statments. simont 7629d 11h /
178 x replaced with 0. simont 7629d 13h /
177 Fix bug in case of writing and reading from same address. simont 7640d 16h /
176 ram modules added. simont 7640d 18h /
175 initial inport. simont 7640d 18h /
174 ram modules added. simont 7640d 18h /
173 simualtion `ifdef added simont 7640d 18h /
172 BIST signals added. simont 7643d 17h /
171 fix bug in DA operation. simont 7651d 15h /
170 removing unused files. simont 7651d 15h /
169 remove unused files. simont 7651d 15h /
168 modify program list. simont 7651d 16h /
167 add readmem for ea. simont 7654d 21h /
166 Change test monitor from ports to external data memory. simont 7655d 14h /
165 remove dumpvars. simont 7655d 19h /
164 initial inport. simont 7655d 19h /
163 initial inport simont 7655d 19h /
162 initial inport. simont 7655d 20h /
161 fix file names. simont 7655d 20h /
160 initial inport. simont 7655d 20h /
159 initial inport. simont 7655d 20h /
158 fix bug. simont 7655d 20h /
157 change data output. simont 7655d 20h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.