URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5477d 15h	/8051/trunk/rtl/verilog/
185		root	5533d 17h	/8051/trunk/rtl/verilog/
181	Simulation reports added.	simont	7612d 09h	/8051/trunk/rtl/verilog/
179	add /* synopsys xx_case */ to case statments.	simont	7612d 10h	/8051/trunk/rtl/verilog/
178	x replaced with 0.	simont	7612d 12h	/8051/trunk/rtl/verilog/
177	Fix bug in case of writing and reading from same address.	simont	7623d 15h	/8051/trunk/rtl/verilog/
175	initial inport.	simont	7623d 17h	/8051/trunk/rtl/verilog/
174	ram modules added.	simont	7623d 17h	/8051/trunk/rtl/verilog/
173	simualtion `ifdef added	simont	7623d 17h	/8051/trunk/rtl/verilog/
172	BIST signals added.	simont	7626d 16h	/8051/trunk/rtl/verilog/
171	fix bug in DA operation.	simont	7634d 14h	/8051/trunk/rtl/verilog/
158	fix bug.	simont	7638d 19h	/8051/trunk/rtl/verilog/
153	`ifdef added.	simont	7640d 13h	/8051/trunk/rtl/verilog/
152	sub_result output added.	simont	7640d 13h	/8051/trunk/rtl/verilog/
151	remove pc_r register.	simont	7640d 13h	/8051/trunk/rtl/verilog/
150	fix some bugs.	simont	7640d 13h	/8051/trunk/rtl/verilog/
149	pipelined acces to axternal instruction interface added.	simont	7640d 13h	/8051/trunk/rtl/verilog/
148	include "8051_defines" added.	simont	7640d 14h	/8051/trunk/rtl/verilog/
146	fix bug in movc intruction.	simont	7662d 14h	/8051/trunk/rtl/verilog/
145	fix bug in case of sequence of inc dptr instrucitons.	simont	7667d 18h	/8051/trunk/rtl/verilog/