URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_acc.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5491d 21h	/8051/trunk/rtl/verilog/oc8051_acc.v
185		root	5547d 22h	/8051/trunk/rtl/verilog/oc8051_acc.v
179	add /* synopsys xx_case */ to case statments.	simont	7626d 15h	/8051/trunk/rtl/verilog/oc8051_acc.v
153	`ifdef added.	simont	7654d 19h	/8051/trunk/rtl/verilog/oc8051_acc.v
118	change wr_sft to 2 bit wire.	simont	7709d 20h	/8051/trunk/rtl/verilog/oc8051_acc.v
117	Register oc8051_sfr dato output, add signal wait_data.	simont	7709d 20h	/8051/trunk/rtl/verilog/oc8051_acc.v
116	change sfr's interface.	simont	7711d 21h	/8051/trunk/rtl/verilog/oc8051_acc.v
82	replace some modules	simont	7795d 22h	/8051/trunk/rtl/verilog/oc8051_acc.v
76	add module oc8051_sfr, 256 bytes internal ram	simont	7864d 19h	/8051/trunk/rtl/verilog/oc8051_acc.v
46	prepared header	simont	7900d 19h	/8051/trunk/rtl/verilog/oc8051_acc.v
38	fix some bugs	simont	7927d 21h	/8051/trunk/rtl/verilog/oc8051_acc.v
37	added signals ack, stb and cyc	simont	7927d 21h	/8051/trunk/rtl/verilog/oc8051_acc.v
22	fix some bugs	simont	7940d 17h	/8051/trunk/rtl/verilog/oc8051_acc.v
5	more linter corrections; 2 tests still fail	markom	7947d 23h	/8051/trunk/rtl/verilog/oc8051_acc.v
4	Code repaired to satisfy the linter; testbech fails	markom	7948d 01h	/8051/trunk/rtl/verilog/oc8051_acc.v
2	Initial CVS import	simont	7963d 23h	/8051/trunk/rtl/verilog/oc8051_acc.v