URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_alu_src_sel.v] - Rev 186

Rev	Log message	Author	Age	Path
186		root	5477d 17h	/8051/trunk/rtl/verilog/oc8051_alu_src_sel.v
185		root	5533d 18h	/8051/trunk/rtl/verilog/oc8051_alu_src_sel.v
179	add /* synopsys xx_case */ to case statments.	simont	7612d 11h	/8051/trunk/rtl/verilog/oc8051_alu_src_sel.v
151	remove pc_r register.	simont	7640d 15h	/8051/trunk/rtl/verilog/oc8051_alu_src_sel.v
141	remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.	simont	7668d 22h	/8051/trunk/rtl/verilog/oc8051_alu_src_sel.v
81	initial import	simont	7781d 18h	/8051/trunk/rtl/verilog/oc8051_alu_src_sel.v