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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_defines.v] - Rev 186

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186 root 5491d 16h /8051/trunk/rtl/verilog/oc8051_defines.v
185 root 5547d 17h /8051/trunk/rtl/verilog/oc8051_defines.v
179 add /* synopsys xx_case */ to case statments. simont 7626d 10h /8051/trunk/rtl/verilog/oc8051_defines.v
174 ram modules added. simont 7637d 18h /8051/trunk/rtl/verilog/oc8051_defines.v
172 BIST signals added. simont 7640d 17h /8051/trunk/rtl/verilog/oc8051_defines.v
149 pipelined acces to axternal instruction interface added. simont 7654d 14h /8051/trunk/rtl/verilog/oc8051_defines.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7682d 21h /8051/trunk/rtl/verilog/oc8051_defines.v
139 add aditional alu destination to solve critical path. simont 7683d 15h /8051/trunk/rtl/verilog/oc8051_defines.v
132 change branch instruction execution (reduse needed clock periods). simont 7693d 14h /8051/trunk/rtl/verilog/oc8051_defines.v
126 define OC8051_XILINX_RAMB added simont 7702d 21h /8051/trunk/rtl/verilog/oc8051_defines.v
122 deifne OC8051_ROM added simont 7707d 21h /8051/trunk/rtl/verilog/oc8051_defines.v
120 defines for pherypherals added simont 7708d 18h /8051/trunk/rtl/verilog/oc8051_defines.v
118 change wr_sft to 2 bit wire. simont 7709d 15h /8051/trunk/rtl/verilog/oc8051_defines.v
114 remove t2mod register simont 7714d 21h /8051/trunk/rtl/verilog/oc8051_defines.v
93 OC8051_XILINX_RAM added simont 7716d 20h /8051/trunk/rtl/verilog/oc8051_defines.v
82 replace some modules simont 7795d 17h /8051/trunk/rtl/verilog/oc8051_defines.v
67 add parameters for instruction cache simont 7876d 18h /8051/trunk/rtl/verilog/oc8051_defines.v
9 removed unused compare states markom 7947d 15h /8051/trunk/rtl/verilog/oc8051_defines.v
2 Initial CVS import simont 7963d 18h /8051/trunk/rtl/verilog/oc8051_defines.v

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